QDRII SRAM (Quad-Data Rate Static Random Access Memory) element is developed for meeting a higher bandwidth storage requirement and aimed at network and telecommunication applications. A basic QDR architecture has independent read data path and written data path so as to facilitate a simultaneous operation. During each clock cycle, both of the paths transmit two words using Double Data Rate (DDR), wherein one is transmitted along the positive edge of the clock, and the other is transmitted along the negative edge of the clock. Data with four bus widths (two for reading and two for writing) will be transmitted in each clock cycle, and this is the origin of the quad-data rate.
There are two common methods for designing the QDR controller, as bellows:
(1) the read data of the QDRII SRAM are synchronized to the system clock domain using asynchronous FIFO (First In First Out), the advantage of this method is simplicity and reliability, and its drawback is long reading delay, which is generally longer than 8 clock cycles;
(2) the read data of the QDRII SRAM are delayed and synchronized to the system clock domain using a programmable delay element, the advantage of this method is short reading delay, which is 6-8 clock cycles in general, and its drawback is that the QDR controller can not be implemented in a case where no programmable delay element is configured by some ASIC factories.